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| Quad Driver Incl. Short-Circuit Signaling FZL 4146 Bipolar IC Features q q q Short-circuit signaling Four driver circuits for driving power transistors Turn-ON threshold setting from 1.5 to 7 V P-DSO-20-7 Type FZL 4146 G General Description Ordering Code Q67000-H8743 Package P-DSO-20-7 (SMD) The IC comprises four driver circuits capable of driving power transistors (PNP or PMOS). The output transistors are protected against short-circuit to ground and supply voltage. The turn-ON threshold can be set from 1.5 V to 7 V. Overload at one or several outputs will be indicated at pin SQ (signaling output). The corresponding power transistors are then protected by changeover to clock-governed operation. Circuit Description Each driver circuit has one active high driver input Dl and a common enable input ENA (active high) is provided for all stages. The Q output is designed to drive the output transistors. The load current is sampled and, if necessary, limited via pin W. If the load current exceeds the preset value, the output stage switches off. Switching-ON again is provided by the built-in clock generator T. Its operation requires an external capacitor Ce at pin CE. If Ce is bridged by a break-key, switching-ON can only be carried out by operating this key. The duty cycle of the clock generator is 1:47 (e.g. 45 s/2.1 ms with Ce = 10 nF). The clock generator is privileged versus the current sensor shut down. When the supply is connected, the internal RS-FF goes into the state corresponding to the released output. Semiconductor Group 1 03.96 FZL 4146 The turn-ON threshold at input Dl and ENA can be set via pin TS from 1.5 to 7 V. VTS = 0 V ... 1.5 V VTS = 1.5 V ... 7 V VTS = VS Turn-ON threshold = 1.5 V Turn-ON threshold = VTS Turn-ON threshold = 7 V Inputs Dl, ENA and W are proof against line break, i.e. an open input at Dl or ENA corresponds to input L, open input W corresponds to overcurrent. If input TS is open, the highest turn-ON threshold is provided. The internal current supply B and the undervoltage monitor UV ensure that in case of a supply voltage that is below the VS turn-OFF threshold, outputs Q and SQ are disabled and the inputs go high-impedance. Basic functioning is possible within the range from VS turn-OFF threshold to 4.5 V. In case of overcurrent or short-circuit to ground at any output stage the signaling output (SQ) will go low. In clock-governed operation (i.e. when there is automatic switching-ON by the clock and not by a key), SQ goes high and low at the clock rate as long as a shortcircuit or overload is present. SQ is an open-collector output. Any input and output is ESD proof within the limit values. Semiconductor Group 2 FZL 4146 Pin Configuration (top view) P-DSO-20-7 Semiconductor Group 3 FZL 4146 Pin Definitions and Functions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol CE ENA DI1 DI2 N.C. GND DI3 DI4 TS SQ W4 Q4 W3 Q3 Function Pin for Ce Enable input for drivers 1 to 4 Input driver 1 Input driver 2 Not connected Ground Input driver 3 Input driver 4 Threshold changeover for all inputs Short-circuit signaling output for drivers 1 to 4 Output current sensor driver 4 Output driver 4 Output current sensor driver 3 Output driver 3 Supply voltage Ground Output current sensor driver 2 Output driver 2 Output current sensor driver 1 Output driver 1 VS GND W2 Q2 W1 Q1 Semiconductor Group 4 FZL 4146 Block Diagram Semiconductor Group 5 FZL 4146 Absolute Maximum Ratings Parameter Symbol Limit Values min. Supply voltage Supply voltage Supply voltage Reverse supply current in GND Input voltage at DI, ENA, TS Input voltage at DI, ENA, TS Output voltage Q Current in Q Voltage at W Voltage at W Voltage at CE Voltage at SQ Input current DI, ENA, TS Input current DI, ENA, TS Input current DI, ENA, TS max. 40 45 48 0.5 40 45 V V V A V V V mA V 100 ms, 5 s interval 120 s 1) 4) Unit Remarks VS VS VS IGND VDI, ENA,TS VDI, ENA,TS VQ IQ VW VW VC VSQ VDI, ENA, TS VDI, ENA, TS VDI, ENA, TS - 0.3 - 0.3 - 0.3 -5 -5 VS - 8 VS 100 ms, 5 s interval min. - 0.3 V 18) 3 - 10 VS - 6.5 VS + 5 VS - 12 - 0.3 - 0.5 -3 -5 - 10 VS + 5 V VS 45 3 5 10 V V mA mA mA min. - 0.3 V, max. 45 min. - 0.3 V, max. 45 V 2) min. - 0.3 V, max. 45 V 3) Output high 4) 100 ms, 5 s interval 10 s, 500 s interval Notes: 1) An adequate resistor in the GND line can provide protection in case of wrong polarization of VS. It should be noted, however, that in this case all pins may become conductive across GND. 2) Loading may lead to degradation and thus to a shift of the switching threshold at W. (Characteristics: switching threshold at W). Short loading may lead to a deviation of approx. 20 mV. 3) In case of short-circuit of V , the capacitance stored in C during previous operation will S e not damage the IC. 4) Note the power loss. Semiconductor Group 6 FZL 4146 Absolute Maximum Ratings (cont'd) Parameter Symbol Limit Values min. Current in SQ Current in W Current in W Junction temperature Storage temperature Therm. resistance, system-ambient Therm. resistance, system-packag. ESD strength acc. to MIL hrs. 883 Meth. 3015 (100 pF/1.5 k, 5 discharges/polarity) Burst strength of the inputs/ outputs Q and W connected to the power transistors (in acc. with IEC publ. 801-4) Junction temperature in normal operation during 15 years with 100 % ED Notes: 5) Unit Remarks max. 8 5 10 150 150 95 25 mA mA mA C C K/W K/W kV 6) ISQ IW IW Tj Tstg Rth SA Rth SP VESD -3 -5 - 10 - 40 - 50 Output low 1 ms, 50 ms interval 5) 10 s, 500 s interval 5) -2 2 VBurst 300 V 7) Tj15 125 C 8) Loading may lead to degradation and thus to a shift of the switching threshold at W. Unfrequent loading leads to a deviation of approx. 20 mV. 6) Related to GND; the GND pins are connected with the chip carrier via the leadframe. 7) If it can be prooved with samples. 8) During normal operation, the failure rate is 100 fit acc. to SN 29500 at a junction temperature of 75 C. Semiconductor Group 7 FZL 4146 Operating Range Parameter Symbol Limit Values min. Supply voltage11) Supply voltage12) Supply voltage13) Supply voltage rise Junction temperature Time-determining capacitor of the clock generator Input voltage Current at output SQ Notes: 9) 10) Unit Remarks max. 40 40 40 1 150 100 40 6 V V V V/s C nF V mA 10) VS VS VS dVS/dt 4.5 VTS + 3 10 -1 - 25 1 -2 -1 VTS = 0 ... 1.5 V VTS = 1.5 ... 7 V VTS = VS 20) Tj Ce VDI, ENA, TS ISQ 14) 15) 16) 17) 19) 11) 12) 13) 14) 15) 16) 17) 18) 19) 20) W pins that remain open, must be connected to VS. The Ce value depends on the desired pulse width tp during short circuit. It applies: Ce = 0.25 mS x tp. At an input threshold = 1.5 V At an input threshold = 1.5 V to 7 V At an input threshold = 7 V This function is also ensured for 40 V VS 45 V and - 40 C Tj - 25 C as long as 0 V VDI, ENA, TS 40 V. The outputs Q are disabled even if - 3 V VDI, ENA - 2 V or - 1 mA IDI, ENA 50 A and VS - 5 V VW VS + 5 V, max. 45 V. The outputs Q are enabled even if 40 V VDI, ENA 45 V and VS - 0.2 V VW VS + 5 V, max. 45 V. Current limiting and disabling of outputs Q are ensured even if 40 V VDI, ENA 45 V and VS - 5 V VW VS - 0.4 V. Dynamic charge reversal of a 2-nF capacitor as in figure 1 is permissible (corresponds to short circuit to conducting output in P-channel MOSFET) Proper working of the IC is also ensured if, before VS is turned-On, an input voltage VDI, ENA is present in the permissible range (footnote 15). At 10 V/s short-term malfunction is possible, but never a latch-up. Semiconductor Group 8 FZL 4146 Characteristics Supply voltage 4.5 V VS 40 V, junction temperature - 25 C Tj 125 C Parameter Symbol Limit Values min. Current consumption Is, OFF Current consumption Is, ON H-input voltage at DI, ENA H-input voltage at DI, ENA L-input voltage at DI, ENA L-input voltage at DI, ENA Input hysteresis typ. max. 5 13.5 mA mA Unit Test Condition VENA = 0 V, Vw = VS 4) VENA = VDI = Vw = VQ = VS; VTS = 0 V3) VTS = 0 V VTS = VS VTS = 0 V VTS = VS 0 V VTS VS 30 V 2 V VTS VS 1.5 V VDI, ENA 30 V 0 V VDI, ENA 30 V VS = 0 V VI H VI H VI L VI L VHI VHI 2 6.8 0.7 4.8 30 30 50 100 100 300 300 200 100 0.5 10 0.6 2 5 1.6 10 100 V V V V mV mV A A V A mA A A Input current DI, ENA1), 7) IDI, ENA Input current DI, ENA IDI0, ENA0 L-output voltage at SQ VSQ L Leakage current output SQ Output current Q Current from TS Current in W Switching threshold at W 2) Notes see page 11. ISQ = 5 mA, VW = VS - 2 V VW = VS VS - 2 V VQ VS VTS = 0.7 V VS - 2 V VW VS ISQ H IQ0 - ITS IW VW VS - 0.25 0.3 VS - VS - V 0.35 Semiconductor Group 9 FZL 4146 Characteristics (cont'd) Supply voltage 4.5 V VS 40 V, junction temperature - 25 C Tj 125 C Parameter Symbol Limit Values min. Current in W Charge current from CE Discharge current from CE Upper switching threshold at CE Lower switching threshold at CE typ. max. 100 5 235 A A A Unit Test Condition IW - ICe VS - 2 V VW VS ICe VCU VCL VQR 6) VQL 6) VS - 0.4 V 2.4 1.4 V V V V VQ at overcurrent VQ at output disable VW = VS - 2 V, IQ = - 20 A VENA = 0 V, IQ = - 20 A, 0 V VS 40 V VS - 0.4 V Signal run time LH Signal run time HL Pulse width Duty cycle tPLH tPHL tP tP/t0 33 1:55 45 50 50 65 s s s Ce = 10 nF Ce = 10 nF 1:47 1:40 10 s s Delay time of the tPWM 5) short-circuit signaling Duration of the tVZ negative spikes at input W, which do not result in switching off Notes see page 11. VC = 0 V 1 Semiconductor Group 10 FZL 4146 Characteristics (cont'd) Supply voltage 4.5 V VS 40 V, junction temperature - 25 C Tj 125 C Parameter Symbol Limit Values min. Difference between VTS and input switching threshold ENA, DI during transition from L to H Idling voltage at output Q typ. max. 0.2 V 2 V VTS 4.8 V Unit Test Condition VDIH - VTS - 0.2 VQH VS - 13 2.5 8 VS - VS - V 11.5 10 4.5 13 19 V k VS 18 V VQ > VQL; IQ = - 20 A VENA = 0 V; IQ = - 100 A RQ = (VS - VQ)/0.1 mA VENA = 0 V; IQ1 = - 3 mA IQ2 = - 8 mA, RQ = VQ/5 mA VS turn-Off threshold VTSV Resistance across Q and VS Z-diode internal resistance RQ RZ 20 50 Footnotes for the Characteristics 1) 2) 3) 4) 5) 6) 7) The given limit values apply to inputs Dl, ENA, if they are not measured, from 0 to 40 V. The layout provides an adaption of Vwtyp. from VS - 0.3 V to VS - 0.4 V or VS - 0.48 V by simply changing of the ALU mask. All inputs Dl1 to Dl4 and W1 to W4 as well as Q1 to Q4 ISON means the sum of all currents flowing from the voltage source VS into the IC, i.e. ISON = IS + IDI + IENA + IW + IQ. All other pins are open. The delay time of loop W I regulator RS-FF AND current source Q is unaccessable for measurement without external wiring due to fast reaction of the current regulator. For this reason, in case of overload, the above mentioned switch-OFF delay time is replaced by the delay time for input W output SQ. Measurement: jump function at W from VW = VS to VW = VS - 1 V IQ = leakage current ICBO of the external PNP-driver transistor For VDI, TS < 1.5 V, IDl, ENA remains below its minimum value; it is however ensured that in case of open inputs the corresponding outputs will be safely disabled. Semiconductor Group 11 FZL 4146 Figure 1 Figure 2 Application Circuit Semiconductor Group 12 FZL 4146 Figure 3 Operating Mode: Automatic Turn-ON after Overload Semiconductor Group 13 FZL 4146 Package Outlines P-DSO-20-7 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Dimensions in mm Semiconductor Group 14 GPS05094 |
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